(a) Field of the Invention
The present invention relates to a method of forming metal wirings for a semiconductor device, and more specifically to forming the metal wirings through a dual damascene process.
(b) Discussion of the Related Art
Typically, in a semiconductor metal wirings are formed from conductive material, such as aluminum, aluminum alloy, copper, or the like. The metal wirings electrically connect the semiconductor devices and pads on a semiconductor substrate.
In order to connect electrodes and pads isolated by dielectric layers formed from oxide, contact holes are formed by selectively etching the dielectric layers. Metal plugs, formed from a barrier metal and tungsten, are used to fill the holes. The metal wirings for contacting the electrodes and the pads are formed by depositing and patterning a metal thin layer.
In order to patterning the metal wirings, a photolithography process is used. As semiconductor devices become more highly integrated, critical dimensions of the metal wirings become more narrow, and it becomes more difficult to form the fine pattern metal wirings.
A dual damascene process is used in an attempt to overcome these problems. In the dual damascene process, a metal wiring layer is patterned by forming a tungsten plug in the contact hole of the dielectric layer, depositing an upper dielectric layer (such as oxide layer) on the dielectric layer, removing the upper dielectric layer on the area at which the metal wiring pattern is formed, depositing a metal thin layer thereon, and planarizing the metal thin layer.
Recently, a dual damascene process has been developed for forming the metal wirings which contact a low conductive layer without forming the metal plug. In this dual damascene process, the contact hole and a trench are formed by sequentially depositing an etch stop layer and a dielectric layer. An etching process is used to selectivity etch the etch stop layer and the dielectric layer. A barrier metal is deposited inside the contact hole and the trench to form the metal wirings, which are formed from copper, for example.
However, this dual damascene technique suffers from disadvantages including that the copper wiring is cracked or detached after the subsequent processes are performed, such as during CMP (chemical mechanical polishing) due to stresses between a fluorine silicate glass (FSG) in the dielectric layer and the copper wirings, as well as because of defective adhesion between the copper wirings and the barrier metal. As a result, a yield of usable semiconductor devices is decreased.